Features of the Imperas Instruction Set Simulator (ISS)
The Imperas ISS is a program executable that is released to run in x86 32 bit Windows/Linux and x64 64 bit Windows/Linux environments.
There are command line arguments that select which processor family and specific processor variant, and which cross compiled application binary are to run.
The ISS implements semi-hosting so that if your C program makes calls to standard newlib functions such as fopen, printf etc, then you need to just compile up your main.c and load it. The ISS semi-hosting intercepts these newlib calls and implements them directly on the host making your cross-compiled application interact directly with the host PC.
- includes the full library of all publicly released Imperas OVP Fast Processor Models
- includes a GDB debugger for each CPU family
- includes the Imperas Graphical User Interface (iGui) to provide full source code debug
- configurable trace subsystem to provide instruction and register tracing
- loads .elf file binaries directly
- allows one instance of a single or multi-core CPU with full memory construction
- uses built in semi-hosting to support library functions such as printf and fopen, and can access host native resources
- can be run interactively or in script/batch mode for regression testing
- includes Imperas Just-In-Time (JIT) Code Morphing high performance CPU simulator technology
- works with Eclipse/CDT GUI
The Imperas Instruction Set Simulator (ISS) includes a GUI and debugger
An Example run of the Imperas Instruction Set Simulator (ISS)
Currently available Instruction Set Simulator (ISS) Families.