Instruction Set Simulator (ISS) Information

This page provides detailed information about the Imperas Instruction Set Simulator for the ARM Cortex-M0plus processor core.
Processor IP owner is ARM Holdings. More information is available from them here.

The Imperas Instruction Set Simulator (ISS) is a product of Imperas Software Ltd. It is a binary licensed by Imperas as a commercial product. It is also available in OVP packages for evaluation and demonstration.

The Imperas ISS uses the OVP Fast Processor Models and dynamically loads them as selected.The OVP Fast Processor Models are written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The processor models are provided as a binary shared object and are also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The models have been run through an extensive QA and regression testing process.

If you develop your own processor models using the OVP VMI APIs then they can be used with the Imperas ISS.

Parallel Simulation using Imperas QuantumLeap
Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools
This ISS executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The ISS also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Overview of ARM Cortex-M0plus Fast Processor Model
This ISS uses the CPU with Model Variant name: Cortex-M0plus
Description:
    ARMM Processor Model
Licensing:
    Usage of binary model under license governing simulator usage.
    
    Note that for models of ARM CPUs the license includes the following terms:
    
    Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
    
    If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
    
    Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
    
    The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
    
    The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
    
    The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
    
    Source of model available under separate Imperas Software License Agreement.
Limitations:
    Performance Monitors are not implemented.
    Debug Extension and related blocks are not implemented.
Verification:
    Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
Features:
    The model is configured with 16 interrupts and 2 priority bits (use override_numInterrupts parameter to change the number of interrupts; the number of priority bits is fixed in this profile).
    MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
    SysTick timer is present. Use parameter SysTickPresent to disable it if required.
    Unprivileged/Privileged Extension is present. Use parameter unprivilegedExtension to disable it if required.
    VTOR register is present. Use parameter VTORPresent to disable it if required.
Unpredictable Behavior:
    Many instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.
Equal Target Registers:
    Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.
Floating Point Load/Store Multiple Lists:
    Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.
If-Then (IT) Block Constraints:
    Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.
Use of R13:
    Use of R13 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows R13 to be used like any other GPR.
Use of R15:
    Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
    Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
    Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
    Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
    Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed.
    Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
    In this variant, the default value of "unpredictableR15" is "execute".

The ISS is downloadable (needs registration and to be logged in) in package Demo_Processors for Windows32 and for Linux32. Note that the ISS is also available for 64 bit hosts as part of the commercial products from Imperas.

The CPU model being used is downloadable (needs registration and to be logged in) in package armm.model for Windows32 and for Linux32. Note that the CPU model is also available for 64 bit hosts as part of the commercial products from Imperas.

OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the OVP simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.

OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant (Cortex-M0plus) being used in this ISS is available OVP_Model_Specific_Information_armm_Cortex-M0plus.pdf.

For more information on the Imperas ISS see the Imperas site and on the OVP Fast Processor model see the OVPworld site.

Configuration
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/armm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

Other Sites/Pages with similar information

Information on the Cortex-M0plus OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: VMI Memory Modeled Component (VMI MMC) API Reference Guide
http://www.ovpworld.org: Debugging with Imperas eGui running on OVP platforms

Two Videos on these models (from other sites)
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development

Currently available Instruction Set Simulator (ISS) Families.

ISS FamilyInstruction Set Simulator (ISS) Variant
RISC-V ISS    RISC-V ISS aliases RV32I RV32IM RV32IMC RV32IMAC RV32G RV32GC RV32GCN RV32E RV32EC RV64I RV64IM RV64IMC RV64IMAC RV64G RV64GC RV64GCN (aliases)
MIPS ISS    MIPS ISS aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 I6500 (aliases)
ARM ISS    ARM ISS aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A32MPx1 Cortex-A32MPx2 Cortex-A32MPx3 Cortex-A32MPx4 Cortex-A35MPx1 Cortex-A35MPx2 Cortex-A35MPx3 Cortex-A35MPx4 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A55MPx1 Cortex-A55MPx2 Cortex-A55MPx3 Cortex-A55MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 Cortex-A73MPx1 Cortex-A73MPx2 Cortex-A73MPx3 Cortex-A73MPx4 Cortex-A75MPx1 Cortex-A75MPx2 Cortex-A75MPx3 Cortex-A75MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
POWER ISS    POWER ISS aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas ISS    Renesas ISS aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
Other ISS    Other ISS aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Andes_N25 Andes_NX25 Microsemi_CoreRISCV Microsemi_MiV_RV32IMA SiFive_E31 SiFive_E51 SiFive_U54 Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)